Cadence Digital and Custom/Analog Design Flows Achieve Certification for TSMC’s Latest N4P and N3E Processes

SAN JOSE, California–(BUSINESS WIRE)–Cadence Design Systems, Inc. (Nasdaq: CDNS) announced today that TSMC has certified Cadence® digital and custom/analog design flows for the latest TSMC N4P and N3E processes to support the new Design Rule Manual (DRM) and FINFLEX Technology. Through continued collaboration, the companies have also provided the appropriate N4P and N3E process design kits (PDKs) to accelerate design innovation for advanced mobile, AI, and hyperscale computing nodes. Customers have already started using the latest TSMC process technologies and certified Cadence streams to achieve optimal performance, power and area (PPA) targets and reduce time to market.

Latest N4P and N3E Digital full-flow certification

Cadence and TSMC R&D teams worked closely to ensure the digital flow met TSMC’s advanced N4P and N3E certification requirements. Cadence’s complete RTL-to-GDS flow includes InnovusImplementation System, QuantusExtraction solution, Quantus FS Solution, Tempus Timing signoff solution and ECO option, Pegasus Verification System, Liberate Characterization Solution, Voltus IC Power Integrity Solution and Voltus-Fi Custom Power Integrity Solution. The Cadence genus Synthesis Solution and iSpatial predictive technology are also enabled for TSMC N4P and N3E process technologies.

The digital full-flow offers several key features that support TSMC N4P and N3E process technologies, including native mixed-height cell line optimization from synthesis to signoff Engineering Change Orders (ECOs) for optimal PPA; row-based default cell placement; Implementation results that correlate well with release for faster design completion; enhanced with column support for better design performance; large libraries with many cells with multiple heights, voltage thresholds (VT) and drive strength; Characterization and analysis of cell timing robustness; Reliability modeling with aging-aware STA; and CCSP model improvements that provide improved accuracy and simplified characterization for analysis via the Voltus IC Power Integrity Solution.

Latest custom/analog flow certification from N4P and N3E

The cadence virtuoso® Design Platform – which includes the Virtuoso Schematic Editor, the Virtuoso ADE Product Suite and the Virtuoso Layout Suite – and Spectre® The simulation platform, which includes the Specter X Simulator, Specter Accelerated Parallel Simulator (APS), Specter eXtensive Partitioning Simulator (XPS), and Specter RF Option, has been certified for TSMC N4P and N3E processes. The Virtuoso Design Platform uniquely offers tight integration with the Innovus Implementation System, which extends the implementation methodology of mixed-signal designs via a common database.

The Custom Design Reference Flow (CDRF) has also been enhanced to support the latest N4P and N3E process technologies. The Virtuoso Schematic Editor, the Virtuoso ADE Suite and the integrated Specter® X Simulator helps customers effectively manage corner simulation, statistical analysis, design centering, and circuit optimization. Optimized for efficient layout implementation, Virtuoso Layout Suite uses a line-based implementation methodology with placement, routing, padding, and dummy insertion capabilities; advanced analog migration and layout reuse capability; integrated parasitic extraction and EM-IR tests; and built-in physical verification capabilities.

“By continuing to work closely with Cadence, we ensure customers can leverage our most advanced N4P and N3E technologies and Cadence’s certified digital and custom/analog operations with confidence,” said Dan Kochpatcharin, Head of Design Infrastructure Management Division at TSMC . “This collaborative effort, combining TSMC’s technological advances with Cadence’s leading design solutions, will help our mutual customers meet stringent power and performance requirements and rapidly bring their next-generation silicon innovations to market.”

“Throughout our long-standing collaboration with TSMC, we have remained focused on developing new technologies that enable our mutual customers to achieve their PPA and productivity goals,” said Dr. Chin-Chi Teng, Senior Vice President and General Manager of Cadence’s Digital & Signoff Group. “Our recent collaboration with TSMC reinforces our commitment to helping customers achieve great designs using our processes and TSMC’s advanced technologies, and we continue to be amazed by the innovations they bring forth.”

Cadence’s digital and custom/analog Advanced Node solutions, aligned with TSMC’s N4P and N3E process technologies, support Cadence’s intelligent system design Strategy that enables customers to achieve System-on-Chip (SoC) design excellence. To learn more about Cadence’s Advanced Node solutions, visit

About Cadence

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