SAN JOSE, California–(BUSINESS WIRE)–Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the leading Cadence® integrity™ The 3D IC platform received certification for TSMC’s 3DFabric and met all reference design flow criteria™ Offerings including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®) and system-on-integrated chips (TSMC SoIC™) technologies. As part of the collaboration, the companies worked together to enable Cadence support for TSMC 3DbloxTM Standard to help customers accelerate advanced multi-die package design for 5G, AI, Mobile, Hyperscale Computing and IoT applications.
The Cadence Integrity 3D IC platform combines system design, implementation, and Cadence Allegro® X-Packaging technologies and system-level analysis and is the industry-leading full-flow platform enabled for TSMC’s new 3Dblox standard, which accelerates 3D front-end design partitioning in complex systems. 3Dblox streamlines key aspects of design methodologies and enables chiplet reuse, providing a seamless interface to Cadence system analysis tools for early Power Delivery Networks (PDN) and thermal analysis via Cadence Voltus™ IC Power Integrity Solution and Celsius™ Thermal solver, extraction and static timing analysis via the Cadence Quantus™ Extraction Solution and Tempus™ Timing signoff resolution and system level (LVS) layout comparison checks via Cadence Pegasus™ verification system. Cadence’s new Allegro Substrate Router (ASR) technology is integrated with Allegro X-Packaging technologies for ultra-high-density die-to-die and die-to-package RDL auto-routing.
“In today’s electronics market, customers need every advantage they can get when designing the advanced 3D ICs that power new application areas,” said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. “By working to ensure that the Cadence Integrity 3D IC platform is certified for use with TSMC 3DFabric technologies, our mutual customers can benefit from significant improvements in design efficiencies that will help them realize advanced multi-chip solutions.” to bring to market quickly.”
“Our Integrity 3D IC platform provides system-level system planning, packaging, and analysis on a single platform that provides customers with seamless design creation capabilities and a comprehensive signoff flow that supports TSMC’s 3DFabric offerings,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “By continuing to work with TSMC, we offer our customers an efficient way to take advantage of the latest developments in 3D chip and multi-die technologies without compromising time to market.”
The Cadence Integrity 3D IC platform is part of the company’s broader 3D IC offering and aligns with Cadence Intelligent System Design™ Strategy that enables excellent System-on-Chip (SoC) design. For more information on the Integrity 3D IC platform, visit www.cadence.com/go/integrityadv3dicpr.
Cadence is a leader in the design of electronic systems, building on more than 30 years of experience in computer software. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and intellectual property that translates design concepts into reality. Cadence customers are the world’s most innovative companies, delivering exceptional electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, cellular, aerospace, consumer, industrial and healthcare. Fortune magazine has named Cadence one of its top 100 places to work for eight consecutive years. Learn more at cadence.com.
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