Inflated processes: TSMC planning chips three times larger than today

TSMC is developing a new version of its Chip-On-Wafer-On-Substrate-L (CoWoS-L) that will allow it to build extremely large interposers – called Super Carrier Interposers – that push the boundaries of current system-in -Packet Sizes (SiPs) to unprecedented levels. Next-gen CoWoS technology, scheduled to qualify in 2025, will potentially increase the size of interposers to as many as six reticle sixes, up to 3.3x what they can do today.

This push toward larger chip sizes is being driven by increasing global demand for advanced computing capabilities in applications such as artificial intelligence (AI) and high-performance computing (HPC). Big players like AMD, Intel and Nvidia are responding to this demand by developing highly complex processors like Nvidia’s H100, which sell for around $30,000 per unit.

To boost the processing power of these processors, these companies use multi-tile chiplet designs: AMD’s Instinct 250X/MI300 as well as Intel’s Ponte Vecchio, which are large and require extremely advanced cooling, are examples of such designs.

The new version of TSMC’s CoWoS-L technology opens new doors by enabling the construction of even larger processors. The size of the CoWoS-L technology is massive considering the reticle limit of ASML’s theoretical EUV tool of 858mm^2. With six reticles, these could allow for SiPs as large as 5148mm^2.

But not only would such solutions accommodate a significant number of large computing chiplets, but such devices would also require fairly large memory subsystems. TSMC speaks of 12 stacks of HBM3/4 storage, which in the case of HBM3 means a storage interface with a bandwidth of close to 9.8 TB/s.

However, building such large SiPs is a daunting task with significant cost implications. To put it in perspective, NVIDIA’s H100 accelerator, which is already several crosshairs in size, costs about $30,000. With this in mind, larger and more powerful chips designed using CoWoS-L technology would no doubt cost significantly more.

In addition to the financial aspect of the chips themselves, there is another major challenge: cooling. The SiPs would be among the most powerful HPC chips to date, which would require advanced cooling systems to prevent overheating. TSMC has researched on-chip liquid cooling technology and demonstrated its ability to cool silicon packages with powers up to 2.6 kW. This could potentially meet the cooling needs of these impressive chips, but adds another level of complexity and expense to the process.