After hours on Friday, Intel released information on a “streamlined and simplified” GPU roadmap for data centers with a direct impact on HPC and AI. The new plan calls for the discontinuation of the “Rialto Bridge” GPU, which was supposed to replace the Ponte Vecchio chip, which itself was delayed by several years before shipments began last year.
In its place, Intel said it would move to a two-year cadence for data center GPUs, starting in 2025 with “Falcon Shores,” part of the Max-series GPUs that officially launched two months ago.
“We’ve simplified our roadmap with the goal of doing less things better and getting our products to our customers quickly,” said Jeff McVeigh, Intel’s corporate VP and interim GM, Accelerated Computing Systems and Graphics, in a blog post Friday.
The announcement continues an unsettled Intel roadmap that stretches back about five years in its portfolio of advanced data center chips as the company struggles to keep up with increasing competition from chip companies NVIDIA and AMD. Delays in the development of Ponte Vecchio and Sapphire Rapids’ 4th generation Xeon Scalable CPU, in turn, led to the installation of the exascale supercomputer Aurora at Argonne National Laboratory being blocked.
While Argonne officials have been optimistic about the ongoing Aurora installation, the updated schedule calls for the system to be open to early researchers by Q3 2023. The Department of Energy’s original exascale plan had Aurora, with Intel as the prime contractor, set to become the first exaFLOP-class system in 2021. Instead, this milestone was achieved by the HPE-built, AMD-powered Frontier supercomputer at Oak Ridge National Laboratory.
McVeigh stated that Rialto Bridge “should offer incremental improvements over our current architecture,” McVeigh said, “with the goal of maximizing return on investment for customers, we will move to a two-year cadence for data center GPUs. This meets customer expectations for new product launches and gives time to develop their ecosystems.”
He said Falcon Shores will have a flexible chiplet-based architecture suitable for AI, HPC and the convergence of the two markets. “This underlying architecture provides the flexibility to integrate new IP (including CPU cores and other chiplets) from Intel and customers over time manufactured using our IDM 2.0 model.”